--
-- VHDL Architecture equalizer_3000_lib.stereo_mono.arch
--
-- Created:
--          by - erial674.student (southfork-08.edu.isy.liu.se)
--          at - 16:18:34 10/11/11
--
-- using Mentor Graphics HDL Designer(TM) 2008.1 (Build 17)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;

ENTITY stereo_mono IS
  port (fpga_clk        : in  std_logic;
        fpga_reset_n    : in  std_logic;
        read_on_change  : in  std_logic;
        left_sample     : in  std_logic_vector (23 downto 0);
        right_sample    : in  std_logic_vector (23 downto 0);
        mono_sample     : buffer integer range -8388608 to 8388607;
        new_data        : out std_logic);
        
END ENTITY stereo_mono;

--
ARCHITECTURE arch OF stereo_mono IS
BEGIN
  
  process(fpga_reset_n, fpga_clk)
    variable old_read_on_change : std_logic;
    begin
    
    if fpga_reset_n = '0' then
      old_read_on_change := '0';
      new_data <= '0';
      
    elsif rising_edge(fpga_clk) then
      
      if read_on_change /= old_read_on_change and read_on_change = '1' then
        mono_sample <= to_integer(signed(right_sample)/2);-- + to_integer(signed(left_sample));
        new_data <= '1';
        
      else
        new_data <= '0';
        
      end if;
      
      old_read_on_change := read_on_change;
    end if;
  end process;
  
END ARCHITECTURE arch;

